AVR Embedded
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AVR Assembly Basics

General syntax: INSTRUCTION Destination, Source

Core Instructions:

• LDI Rd, K: Load constant K (0-255) into Rd (R16-R31).
• LDS Rd, k: Load byte from SRAM address k (16-bit address).
• STS k, Rr: Store register Rr byte to SRAM address k.
• IN Rd, A: Read byte from I/O register A (address 0-63).
• OUT A, Rr: Write register Rr to I/O register A (address 0-63).
• MOV Rd, Rr: Copy register Rr to Rd.
• ADD Rd, Rr: Add Rr to Rd (updates SREG flags: C, Z, N, V, H).
• SUB Rd, Rr: Subtract Rr from Rd (updates flags).
• INC Rd / DEC Rd: Increment / Decrement register Rd.
• CP Rd, Rr: Compare Rd with Rr (performs subtraction, updates flags, doesn't write back Rd).

SREG (Status Register) Flags: I T H S V N Z C (C=Carry, Z=Zero, N=Negative, V=Overflow, S=Sign, H=Half-Carry, I=Global Interrupt Enable).

📋 Data Transfer Instructions (from Exam Sheet)

Mnemonic	Operands	Description	Operation	Flags
MOV	Rd, Rr	Copy Register	Rd ← Rr	None
MOVW	Rd, Rr	Copy Register Word	Rd+1:Rd ← Rr+1:Rr	None
LDI	Rd, K	Load Immediate (R16-R31)	Rd ← K	None
LDS	Rd, k	Load Direct from SRAM	Rd ← (k)	None
STS	k, Rr	Store Direct to SRAM	(k) ← Rr	None
LD	Rd, X / X+ / -X	Load Indirect using X Pointer	Rd ← (X), post-inc or pre-dec	None
LD	Rd, Y / Y+ / -Y	Load Indirect using Y Pointer	Rd ← (Y), post-inc or pre-dec	None
LDD	Rd, Y+q	Load Indirect with Displacement	Rd ← (Y + q)	None
LD	Rd, Z / Z+ / -Z	Load Indirect using Z Pointer	Rd ← (Z), post-inc or pre-dec	None
LDD	Rd, Z+q	Load Indirect with Displacement	Rd ← (Z + q)	None
ST	X / X+ / -X, Rr	Store Indirect using X Pointer	(X) ← Rr, post-inc or pre-dec	None
ST	Y / Y+ / -Y, Rr	Store Indirect using Y Pointer	(Y) ← Rr, post-inc or pre-dec	None
STD	Y+q, Rr	Store Indirect with Displacement	(Y + q) ← Rr	None
ST	Z / Z+ / -Z, Rr	Store Indirect using Z Pointer	(Z) ← Rr, post-inc or pre-dec	None
STD	Z+q, Rr	Store Indirect with Displacement	(Z + q) ← Rr	None
LPM	None / Rd, Z / Rd, Z+	Load Program Memory	Rd ← (Z), post-inc option	None
SPM	None	Store Program Memory	(Z) ← R1:R0	None
IN	Rd, P	In Port / Read I/O Port	Rd ← P	None
OUT	P, Rr	Out Port / Write I/O Port	P ← Rr	None
PUSH	Rr	Push Register on Stack	Stack ← Rr	None
POP	Rd	Pop Register from Stack	Rd ← Stack	None

📋 Arithmetic and Logic Instructions (from Exam Sheet)

Mnemonic	Operands	Description	Operation	Flags
ADD	Rd, Rr	Add registers	Rd ← Rd + Rr	Z, C, N, V, H
ADC	Rd, Rr	Add with Carry registers	Rd ← Rd + Rr + C	Z, C, N, V, H
ADIW	Rdl, K	Add Immediate to Word	Rdh:Rdl ← Rdh:Rdl + K	Z, C, N, V, S
SUB	Rd, Rr	Subtract registers	Rd ← Rd - Rr	Z, C, N, V, H
SUBI	Rd, K	Subtract Immediate from register	Rd ← Rd - K	Z, C, N, V, H
SBC	Rd, Rr	Subtract with Carry registers	Rd ← Rd - Rr - C	Z, C, N, V, H
SBCI	Rd, K	Subtract with Carry Immediate	Rd ← Rd - K - C	Z, C, N, V, H
SBIW	Rdl, K	Subtract Immediate from Word	Rdh:Rdl ← Rdh:Rdl - K	Z, C, N, V, S
AND	Rd, Rr	Logical AND registers	Rd ← Rd • Rr	Z, N, V
ANDI	Rd, K	Logical AND register with Immediate	Rd ← Rd • K	Z, N, V
OR	Rd, Rr	Logical OR registers	Rd ← Rd v Rr	Z, N, V
ORI	Rd, K	Logical OR register with Immediate	Rd ← Rd v K	Z, N, V
EOR	Rd, Rr	Exclusive OR registers	Rd ← Rd ⊕ Rr	Z, N, V
COM	Rd	One's Complement (Bitwise NOT)	Rd ← 0xFF - Rd	Z, C, N, V
NEG	Rd	Two's Complement (Negate)	Rd ← 0x00 - Rd	Z, C, N, V, H
SBR	Rd, K	Set Bits in Register	Rd ← Rd v K	Z, N, V
CBR	Rd, K	Clear Bits in Register	Rd ← Rd • (0xFF - K)	Z, N, V
INC	Rd	Increment	Rd ← Rd + 1	Z, N, V
DEC	Rd	Decrement	Rd ← Rd - 1	Z, N, V
TST	Rd	Test for Zero or Minus	Rd ← Rd • Rd	Z, N, V
CLR	Rd	Clear Register	Rd ← 0x00	Z, N, V
SER	Rd	Set Register (All ones)	Rd ← 0xFF	None
MUL	Rd, Rr	Multiply Unsigned	R1:R0 ← Rd × Rr	Z, C
MULS	Rd, Rr	Multiply Signed	R1:R0 ← Rd × Rr	Z, C
MULSU	Rd, Rr	Multiply Signed with Unsigned	R1:R0 ← Rd × Rr	Z, C

Jump & Call Instructions (Program Flow)

Unconditional Jumps:

• RJMP k: Relative jump (offset ±2K instructions, 2-byte instruction, 2 cycles).
• JMP k: Absolute jump to 22-bit address (4-byte instruction, 3 cycles).
• IJMP: Indirect jump (jumps to the address stored in the Z register R31:R30).

Subroutine Calls:

• RCALL k / CALL k: Pushes Program Counter (PC) (2 bytes) onto Stack, decrements SP by 2, then jumps.
• RET: Return from subroutine. Pops 2 bytes from Stack into PC, increments SP by 2.
• RETI: Return from Interrupt Service Routine. Same as RET but also sets SREG global interrupt bit (I = 1) automatically.

Stack Pointer Initialization (RAMEND = 0x08FF):

Conditional Branches: BREQ k (branch if Z=1), BRNE k (branch if Z=0), BRCS k (branch if C=1), BRCC k (branch if C=0). Relative offset range: -64 to +63 instructions.

📋 Branch & Jump Instructions (from Exam Sheet)

Mnemonic	Operands	Description	Operation	Flags
RJMP	k	Relative Jump	PC ← PC + k + 1	None
JMP	k	Direct Absolute Jump	PC ← k	None
IJMP	None	Indirect Jump to (Z)	PC ← Z (R31:R30)	None
RCALL	k	Relative Subroutine Call	PC ← PC + k + 1, push Stack	None
CALL	k	Direct Absolute Subroutine Call	PC ← k, push Stack	None
ICALL	None	Indirect Call to (Z)	PC ← Z, push Stack	None
RET	None	Subroutine Return	PC ← Stack	None
RETI	None	Interrupt Return	PC ← Stack, SREG I ← 1	I
CPSE	Rd, Rr	Compare, Skip if Equal	if (Rd == Rr) PC ← PC + 2 or 3	None
CP	Rd, Rr	Compare	Rd - Rr	Z, N, V, C, H
CPC	Rd, Rr	Compare with Carry	Rd - Rr - C	Z, N, V, C, H
CPI	Rd, K	Compare Register with Immediate	Rd - K	Z, N, V, C, H
SBRC	Rr, b	Skip if Bit in Register is Cleared	if (Rr(b)==0) PC ← PC + 2 or 3	None
SBRS	Rr, b	Skip if Bit in Register is Set	if (Rr(b)==1) PC ← PC + 2 or 3	None
SBIC	P, b	Skip if Bit in I/O Reg is Cleared	if (P(b)==0) PC ← PC + 2 or 3	None
SBIS	P, b	Skip if Bit in I/O Reg is Set	if (P(b)==1) PC ← PC + 2 or 3	None
BRBS	s, k	Branch if Status Flag Set	if (SREG(s)==1) PC ← PC+k+1	None
BRBC	s, k	Branch if Status Flag Cleared	if (SREG(s)==0) PC ← PC+k+1	None
BREQ	k	Branch if Equal	if (Z == 1) PC ← PC + k + 1	None
BRNE	k	Branch if Not Equal	if (Z == 0) PC ← PC + k + 1	None
BRCS / BRLO	k	Branch if Carry Set / Lower	if (C == 1) PC ← PC + k + 1	None
BRCC / BRSH	k	Branch if Carry Clear / Same or Higher	if (C == 0) PC ← PC + k + 1	None
BRMI	k	Branch if Minus (Negative)	if (N == 1) PC ← PC + k + 1	None
BRPL	k	Branch if Plus (Positive)	if (N == 0) PC ← PC + k + 1	None
BRGE	k	Branch if Greater or Equal (Signed)	if (N ⊕ V == 0) PC ← PC + k + 1	None
BRLT	k	Branch if Less Than Zero (Signed)	if (N ⊕ V == 1) PC ← PC + k + 1	None
BRHS	k	Branch if Half Carry Set	if (H == 1) PC ← PC + k + 1	None
BRHC	k	Branch if Half Carry Cleared	if (H == 0) PC ← PC + k + 1	None

GPIO & Bit Fiddling (ATmega328P Port Registers)

Each port (B, C, D) has three registers: DDRx (Direction), PORTx (Output / Pull-up), and PINx (Input Pin Value - Read Only).

DDRx Bit	PORTx Bit	Pin Config	Description
0 (Input)	0	Input, High-Z	Pin is floating (high impedance). Input reading is volatile.
0 (Input)	1	Input, Pull-up	Internal 20K-50K pull-up resistor enabled. Pin idles HIGH.
1 (Output)	0	Output, LOW	Pin is driven to GND (0V). Can sink current.
1 (Output)	1	Output, HIGH	Pin is driven to VCC (5V). Can source current.

Bitwise Trinity in C:

• Set bit: PORTB |= (1 << 5);
• Clear bit: PORTB &= ~(1 << 5);
• Toggle bit: PORTB ^= (1 << 5);
• Read pin: if ((PINB & (1 << 3)) == 0) { ... }

Directives in Assembly: SBI ioreg, bit (Set bit in I/O reg), CBI ioreg, bit (Clear bit), SBIS ioreg, bit (Skip next instruction if I/O bit is set), SBIC ioreg, bit (Skip if clear).

📋 Bit and Bit-Test Instructions (from Exam Sheet)

Mnemonic	Operands	Description	Operation	Flags
SBI	P, b	Set Bit in I/O Register	I/O(P, b) ← 1	None
CBI	P, b	Clear Bit in I/O Register	I/O(P, b) ← 0	None
LSL	Rd	Logical Shift Left	Rd(n+1) ← Rd(n), Rd(0) ← 0	Z, C, N, V
LSR	Rd	Logical Shift Right	Rd(n) ← Rd(n+1), Rd(7) ← 0	Z, C, N, V
ROL	Rd	Rotate Left through Carry	Rd(0) ← C, Rd(n+1) ← Rd(n), C ← Rd(7)	Z, C, N, V
ROR	Rd	Rotate Right through Carry	Rd(7) ← C, Rd(n) ← Rd(n+1), C ← Rd(0)	Z, C, N, V
ASR	Rd	Arithmetic Shift Right	Rd(n) ← Rd(n+1), Rd(7) remains	Z, C, N, V
SWAP	Rd	Swap Nibbles	Rd(3..0) ↔ Rd(7..4)	None
BSET	s	Flag Set in SREG	SREG(s) ← 1	SREG(s)
BCLR	s	Flag Clear in SREG	SREG(s) ← 0	SREG(s)
BST	Rr, b	Store Bit in Register to T Flag	T ← Rr(b)	T
BLD	Rd, b	Load Bit from T Flag to Register	Rd(b) ← T	None
SEC / CLC	None	Set / Clear Carry Flag	C ← 1 / 0	C
SEZ / CLZ	None	Set / Clear Zero Flag	Z ← 1 / 0	Z
SEI / CLI	None	Set / Clear Global Interrupt	I ← 1 / 0	I

Timer / Counter (Truth Tables & Calculations)

Calculations:

• Delay tick:
T_tick =
N_prescaler
f_CPU
• Preload Value (Normal Mode):
Preload = 2ⁿ −
Delay × f_CPU
N_prescaler
(where n = 8 or 16 bits)
• Compare Value (CTC Mode):
OCR =
Delay × f_CPU
N_prescaler
− 1

CTC & Normal Mode Selection Cheat Sheet:

WGM (Waveform Generation Mode) Truth Tables:

Timer 0 and Timer 2 (8-bit):

Mode	WGM02	WGM01	WGM00	Mode Description	TOP	TOV Flag Set on
0	0	0	0	Normal (Upcounting)	0xFF	MAX (0xFF)
2	0	1	0	CTC (Clear Timer on Compare Match)	OCR0A	MAX (0xFF)
3	0	1	1	Fast PWM	0xFF	MAX (0xFF)
7	1	1	1	Fast PWM	OCR0A	TOP

Timer 1 (16-bit):

Mode	WGM13	WGM12	WGM11	WGM10	Mode Description	TOP	TOV Flag Set on
0	0	0	0	0	Normal (Upcounting)	0xFFFF	MAX (0xFFFF)
4	0	1	0	0	CTC (Clear Timer on Compare Match)	OCR1A	MAX (0xFFFF)
14	1	1	1	0	Fast PWM	ICR1	TOP
15	1	1	1	1	Fast PWM	OCR1A	TOP

Clock Source / Prescaler Selector (CS02:CS00 for Timer 0 & 1):

CSn2	CSn1	CSn0	Prescaler / Clock Source Selection
0	0	0	No clock source (Timer/Counter stopped)
0	0	1	clk_I/O (No prescaling)
0	1	0	clk_I/O / 8
0	1	1	clk_I/O / 64
1	0	0	clk_I/O / 256
1	0	1	clk_I/O / 1024
1	1	0	External clock on Tn pin (Falling Edge)
1	1	1	External clock on Tn pin (Rising Edge)

Interrupts (Vectors & Registers)

Registers:

• SREG (bit 7 - I): Global Interrupt Enable. Set by sei(), cleared by cli().
• EIMSK: External Interrupt Mask Register (bit 0 = INT0 enable, bit 1 = INT1 enable).
• EICRA: External Interrupt Control Register A. Configures trigger edges:

ISCn1	ISCn0	Trigger Mode Description
0	0	Low level of INTn pin generates interrupt request
0	1	Any logical change on INTn pin generates interrupt request
1	0	Falling edge of INTn pin generates interrupt request
1	1	Rising edge of INTn pin generates interrupt request

Selected Vector Table Addresses (in Flash):

• Reset: 0x0000
• INT0: 0x0002
• INT1: 0x0004
• TIMER1 COMPA: 0x0016
• TIMER1 OVF: 0x001A
• TIMER0 OVF: 0x0020

UART / Serial Communication (USART0)

Baud Rate Divisor Formulas (Async Normal Mode, U2X0 = 0):

Baud Rate Divisor Formulas (Async Double Speed Mode, U2X0 = 1):

Core Registers:

• UDR0: USART Data Register (Read = RX buffer, Write = TX buffer).
• UCSR0A: Status register. Bits: RXC0 (Receive Complete flag), TXC0 (Transmit Complete flag), UDRE0 (USART Data Register Empty flag - 1 means ready to accept new byte).
• UCSR0B: Control register B. Bits: RXCIE0 (RX Complete Interrupt Enable), RXEN0 (Receiver Enable), TXEN0 (Transmitter Enable), UCSZ02 (Character Size bit 2).
• UCSR0C: Control register C. Bits: UMSEL01:UMSEL00 (00 = Async, 01 = Sync), UPM01:UPM00 (Parity: 00=None, 10=Even, 11=Odd), USBS0 (Stop bits: 0=1-bit, 1=2-bit), UCSZ01:UCSZ00 (Character size: 11 = 8-bit).

ADC (Analog-to-Digital Converter)

Voltage to Digital Conversion Formula:

Core Registers:

• ADMUX: Channel and Reference Selection.
  • REFS1:REFS0: 00 = AREF pin, 01 = AVCC with capacitor at AREF, 11 = Internal 1.1V ref.
  • ADLAR: Left Adjust Result. (0 = Right adjusted to ADCL/ADCH, 1 = Left adjusted).
  • MUX3:MUX0: Analog Channel Select (0000 = ADC0, 0001 = ADC1, ..., 0101 = ADC5).
• ADCSRA: Control and Status Register A.
  • ADEN: ADC Enable. Must be 1 to use ADC.
  • ADSC: ADC Start Conversion. Write 1 to start conversion.
  • ADIF: ADC Interrupt Flag. Becomes 1 when conversion is complete. Clear by writing 1.
  • ADIE: ADC Interrupt Enable.
  • ADPS2:ADPS0: Prescaler Select bits. Divides system clock to ADC clock (must be between 50kHz and 200kHz for max accuracy). 111 = clk/128, 110 = clk/64.

PWM & DC Motor Control (Not in Exam)

PWM Frequency Formulas:

Duty Cycle Calculations:

Compare Output Mode in Fast PWM (COM0A1:COM0A0):

COM0A1	COM0A0	Compare Output Mode Description
0	0	Normal port operation, OC0A disconnected
1	0	Clear OC0A on Compare Match, set OC0A at BOTTOM (non-inverting mode)
1	1	Set OC0A on Compare Match, clear OC0A at BOTTOM (inverting mode)